A Decision Diagram based Hierarchical Test Pattern Generator

* This work has been supported by the Estonian Science Foundation grant G-1850 ABSTRACT: A hierarchical test generation approach to digital circuits, which uses Register-Transfer (RT) and gate level model descriptions, is presented. The proposed test generator implements a novel test generation technique based on Decision Diagram (DD) models. Uniform modeling procedures are used on both levels, as well as for datapath and control parts. Experimental results show that the method offers better performance than other state-of-the-art test generators for sequential circuits [1, 2, 3].